This course can also be taken for academic credit as ECEA 5361, part of CU Boulder’s Master of Science in Electrical Engineering degree.
FPGA Design for Embedded Systems 특화 과정콜로라도 대학교 볼더 캠퍼스이 강좌에 대하여
최근 조회 36,405회
유연한 마감일
일정에 따라 마감일을 재설정합니다.
공유 가능한 수료증
완료 시 수료증 획득
100% 온라인
지금 바로 시작해 나만의 일정에 따라 학습을 진행하세요.
다음 특화 과정의 4개 강좌 중 2번째 강좌:
중급 단계
완료하는 데 약 36시간 필요
영어
자막: 아랍어, 프랑스어, 포르투갈어 (유럽), 이탈리아어, 베트남어, 독일어, 러시아어, 영어, 스페인어
귀하가 습득할 기술
- Writing Code in Verilog
- Simulating FPGA Designs
- Designing FPGA Logic
- Designing Test Benches
- Writing code in VHDL
유연한 마감일
일정에 따라 마감일을 재설정합니다.
공유 가능한 수료증
완료 시 수료증 획득
100% 온라인
지금 바로 시작해 나만의 일정에 따라 학습을 진행하세요.
다음 특화 과정의 4개 강좌 중 2번째 강좌:
중급 단계
완료하는 데 약 36시간 필요
영어
자막: 아랍어, 프랑스어, 포르투갈어 (유럽), 이탈리아어, 베트남어, 독일어, 러시아어, 영어, 스페인어
제공자:
콜로라도 대학교 볼더 캠퍼스
CU-Boulder is a dynamic community of scholars and learners on one of the most spectacular college campuses in the country. As one of 34 U.S. public institutions in the prestigious Association of American Universities (AAU), we have a proud tradition of academic excellence, with five Nobel laureates and more than 50 members of prestigious academic academies.
석사 학위 취득 시작
이 강좌은(는) 콜로라도 대학교 볼더 캠퍼스의 100% 온라인 Master of Science in Electrical Engineering 중 일부입니다.
전체 프로그램을 수료하면 귀하의 강좌가 학위 취득에 반영됩니다.
강의 계획표 - 이 강좌에서 배울 내용
완료하는 데 8시간 필요
Basics of VHDL
This module introduces the basics of the VHDL language for logic design. It describes the use of VHDL as a design entry method for logic design in FPGAs and ASICs. To provide context, it shows where VHDL is used in the FPGA design flow. Then a simple example, a 4-bit comparator, is used as a first phrase in the language. VHDL rules and syntax are explained, along with statements, identifiers and keywords. Finally, use of simulation as a means of testing VHDL circuit designs is demonstrated using ModelSim, a simulator software tool. Programming assignments are used to develop skills and reinforce the concepts presented.
완료하는 데 8시간 필요
10개 동영상 (총 48분), 3 개의 읽기 자료, 6 개의 테스트
완료하는 데 12시간 필요
VHDL Logic Design Techniques
In this module use of the VHDL language to perform logic design is explored further. Many examples of combinatorial and synchronous logic circuits are presented and explained, including flip-flops, counters, registers, memories, tri-state buffers and finite state machines. Methods of hierarchical design and modular design techniques are explained and demonstrated. How to create test benches is described as a means for design verification. Students are giving ample opportunity to practice and refined their design technique using the programming assignments.
완료하는 데 12시간 필요
10개 동영상 (총 52분), 2 개의 읽기 자료, 6 개의 테스트
완료하는 데 7시간 필요
Basics of Verilog
This module introduces the basics of the Verilog language for logic design. It describes the use of Verilog as a design entry method for logic design in FPGAs and ASICs, including the history of Verilog's development. Then a simple example, a 4-bit comparator, is used as a first phrase in the language. Verilog rules and syntax are explained, along with statements, operators and keywords. Finally, use of simulation as a means of testing Verilog circuit designs is demonstrated using ModelSim, a simulator tool. Programming assignments are used to develop skills and reinforce the concepts presented.
완료하는 데 7시간 필요
9개 동영상 (총 92분), 2 개의 읽기 자료, 6 개의 테스트
완료하는 데 10시간 필요
Verilog and System Verilog Design Techniques
In this module use of the Verilog language to perform logic design is explored further. Many examples of combinatorial and synchronous logic circuits are presented and explained, including flip-flops, counters, registers, memories, tri-state buffers and finite state machines. Methods of hierarchical design and modular design techniques are explained and demonstrated. How to create test benches is described as a means for design verification. Students are giving ample opportunity to practice and refined their design technique by writing code as required by the programming assignments.
완료하는 데 10시간 필요
10개 동영상 (총 48분), 2 개의 읽기 자료, 6 개의 테스트
검토
- 5 stars58.70%
- 4 stars28.38%
- 3 stars6.88%
- 2 stars2.79%
- 1 star3.22%
HARDWARE DESCRIPTION LANGUAGES FOR FPGA DESIGN의 최상위 리뷰
JK 제공2022년 3월 27일
bhut sexy course. mujhe nhi krna ab fir bhi enroll nhi kr paa rha .feeling happy and semd at the same time
AS 제공2022년 1월 15일
good course for getting hands on exposure for learning VHDL and verilog in less time, found it very useful.
AS 제공2020년 5월 6일
FIFO assignments in both Verilog and VHDL should define purpose of all the internal nets and registers listed in the problem.
JP 제공2020년 10월 6일
I think this is a good start in learning how to write VHDL and Verilog. I would like to see a next level course or recommendations for further writing code.
FPGA Design for Embedded Systems 특화 과정 정보
The objective of this course is to acquire proficiency with Field Programmable Gate Arrays (FPGA)s for the purpose of creating prototypes or products for a variety of applications. Although FPGA design can be a complex topic, we will introduce it so that, with a little bit of effort, the basic concepts will be easily learned, while also providing a challenge for the more experienced designer. We will explore complexities, capabilities and trends of Field Programmable Gate Arrays (FPGA) and Complex Programmable Logic Devices (CPLD). Conception, design, implementation, and debugging skills will be practiced. We will learn specifics around embedded IP and processor cores, including tradeoffs between implementing versus acquiring IP. Projects will involve the latest software and FPGA development tools and hardware platforms to help develop a broad perspective of the capabilities of various Programmable SoC solutions. Topics include:
자주 묻는 질문
강의 및 과제를 언제 이용할 수 있게 되나요?
이 전문 분야를 구독하면 무엇을 이용할 수 있나요?
재정 지원을 받을 수 있나요?
궁금한 점이 더 있으신가요? 학습자 도움말 센터를 방문해 보세요.
