이 강좌에 대하여

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This course can also be taken for academic credit as ECEA 5361, part of CU Boulder’s Master of Science in Electrical Engineering degree.
Hardware Description Languages for Logic Design enables students to design circuits using VHDL and Verilog, the most widespread design methods for FPGA Design.   It uses natural learning processes to make learning the languages easy.  Simple first examples are presented, then language rules and syntax, followed by more complex examples, and then finally use of test bench simulations to verify correctness of the designs.  Lecture presentations are reinforced by many programming example problems so that skill in the languages is obtained.  After completing this course, each student will have fundamental proficiency in both languages, and more importantly enough knowledge to continue learning and gaining expertise in Verilog and VHDL on their own.

공유 가능한 수료증

완료 시 수료증 획득

100% 온라인

지금 바로 시작해 나만의 일정에 따라 학습을 진행하세요.

유동적 마감일

일정에 따라 마감일을 재설정합니다.

중급 단계

완료하는 데 약 36시간 필요

영어

자막: 영어

귀하가 습득할 기술

Writing Code in VerilogSimulating FPGA DesignsDesigning FPGA LogicDesigning Test BenchesWriting code in VHDL

공유 가능한 수료증

완료 시 수료증 획득

100% 온라인

지금 바로 시작해 나만의 일정에 따라 학습을 진행하세요.

유동적 마감일

일정에 따라 마감일을 재설정합니다.

중급 단계

완료하는 데 약 36시간 필요

영어

자막: 영어

강의 계획 - 이 강좌에서 배울 내용

주

1

주 1

완료하는 데 8시간 필요

Basics of VHDL

This module introduces the basics of the VHDL language for logic design. It describes the use of VHDL as a design entry method for logic design in FPGAs and ASICs. To provide context, it shows where VHDL is used in the FPGA design flow. Then a simple example, a 4-bit comparator, is used as a first phrase in the language. VHDL rules and syntax are explained, along with statements, identifiers and keywords. Finally, use of simulation as a means of testing VHDL circuit designs is demonstrated using ModelSim, a simulator software tool. Programming assignments are used to develop skills and reinforce the concepts presented.

완료하는 데 8시간 필요

10개 동영상 (총 48분), 2 개의 읽기 자료, 6 개의 테스트

10개의 동영상

Introduction to Hardware Description Languages for FPGA Design4m

Why Learn VHDL?1m

FPGA Design Flow3m

Intro to VHDL: Finite State Machine3m

How to speak VHDL, first phrases6m

VHDL Assignments, Operators, Types3m

VHDL Rules and Syntax, Interface Ports3m

VHDL in ModelSim: Download and Install3m

VHDL in ModelSim: Adding to your Toolkit6m

Submitting VHDL Programming Assignments11m

2개의 읽기 자료

Misson 2-001: Week 1 Readings2시간

Files for Week 1 Programming Assignments10m

2개 연습문제

VHDL Find the Code Errors30m

Module 1 Quiz30m

주

2

주 2

완료하는 데 12시간 필요

VHDL Logic Design Techniques

In this module use of the VHDL language to perform logic design is explored further. Many examples of combinatorial and synchronous logic circuits are presented and explained, including flip-flops, counters, registers, memories, tri-state buffers and finite state machines. Methods of hierarchical design and modular design techniques are explained and demonstrated. How to create test benches is described as a means for design verification. Students are giving ample opportunity to practice and refined their design technique using the programming assignments.

완료하는 데 12시간 필요

10개 동영상 (총 52분), 2 개의 읽기 자료, 6 개의 테스트

10개의 동영상

Learning to speak VHDL (Intro)1m

Combinatorial Circuits4m

Synchronous Logic: Latches and Flip Flops4m

Synchronous Logic: Counters and Registers6m

Buses and Tristate Buffers3m

Modular Designs: Components, Generate and Loops in VHDL3m

Test Benches in VHDL: Combinatorial8m

Test Benches in VHDL: Synchronous5m

Memory in VHDL7m

Finite State Machines in VHDL8m

2개의 읽기 자료

Week 2 Readings2시간

Files for Week 2 Programming Assignments10m

1개 연습문제

Module 2 Quiz30m

주

3

주 3

완료하는 데 7시간 필요

Basics of Verilog

This module introduces the basics of the Verilog language for logic design. It describes the use of Verilog as a design entry method for logic design in FPGAs and ASICs, including the history of Verilog's development. Then a simple example, a 4-bit comparator, is used as a first phrase in the language. Verilog rules and syntax are explained, along with statements, operators and keywords. Finally, use of simulation as a means of testing Verilog circuit designs is demonstrated using ModelSim, a simulator tool. Programming assignments are used to develop skills and reinforce the concepts presented.

완료하는 데 7시간 필요

9개 동영상 (총 92분), 2 개의 읽기 자료, 6 개의 테스트

9개의 동영상

Verilog for fun and profit (intro)3m

Your First Verilog phrase11m

Verilog Rules and Syntax; Keywords and Identifiers; Sigasi/Quartus editing12m

Verilog Statements and Operators16m

Verilog Modules, Port Modes and Data Types10m

Verilog Structure10m

Testing with ModelSim5m

Verilog Evaluation11m

Submitting Verilog Programming Assignments10m

2개의 읽기 자료

Week 3 Readings1시간 10분

Files for Week 3 Programming Assignments10m

2개 연습문제

Verilog Find the Errors20m

Module 3 Quiz30m

주

4

주 4

완료하는 데 10시간 필요

Verilog and System Verilog Design Techniques

In this module use of the Verilog language to perform logic design is explored further. Many examples of combinatorial and synchronous logic circuits are presented and explained, including flip-flops, counters, registers, memories, tri-state buffers and finite state machines. Methods of hierarchical design and modular design techniques are explained and demonstrated. How to create test benches is described as a means for design verification. Students are giving ample opportunity to practice and refined their design technique by writing code as required by the programming assignments.

완료하는 데 10시간 필요

10개 동영상 (총 48분), 2 개의 읽기 자료, 6 개의 테스트

10개의 동영상

Learning to speak Verilog (intro)3m

Combinatorial Circuits5m

Synchronous Logic: Latches and Flip Flops3m

Synchronous Logic: Counters and Registers5m

Buses and Tristate Buffers3m

Modular Design in Verilog3m

Testbenches in Verilog7m

Testbenches in Verilog II2m

Memory with Verilog4m

Verilog Finite State Machines7m

2개의 읽기 자료

Week 4 Readings15m

Files for Week 4 Programming Assignments10m

1개 연습문제

Module 4 Quiz30m

자주 묻는 질문

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Hardware Description Languages for FPGA Design