About this Course
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지금 바로 시작해 나만의 일정에 따라 학습을 진행하세요.

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일정에 따라 마감일을 재설정합니다.

중급 단계

완료하는 데 약 12시간 필요

영어

자막: 영어

100% 온라인

지금 바로 시작해 나만의 일정에 따라 학습을 진행하세요.

유동적 마감일

일정에 따라 마감일을 재설정합니다.

중급 단계

완료하는 데 약 12시간 필요

영어

자막: 영어

강의 계획 - 이 강좌에서 배울 내용

1
완료하는 데 1시간 필요

Orientation

In this module you will become familiar with the course and our learning environment. The orientation will also help you obtain the technical skills required for the course.

...
2 videos (Total 23 min), 2 readings, 1 quiz
2개의 읽기 자료
Syllabus10m
Tools For This Course10m
1개 연습문제
Demographics Survey5m
완료하는 데 3시간 필요

ASIC Placement

In this second part of our course, we will talk about geometry. We will begin with an overview of the ASIC layout process, and discuss the role of technology libraries, tech mapping (a topic we delay until the following week, to let those who want to do the Placer programming assignment have more time), and placement and routing. In this set of lectures, we focus on the placement process itself: you have a million gates from the result of synthesis and map, so, where do they go? This process is called “placement”, and we describe an iterative method, and a mathematical optimization method, that can each do very large placement tasks.

...
9 videos (Total 163 min), 2 readings
9개의 동영상
Iterative Improvement with Hill Climbing15m
Simulated Annealing Placement27m
Analytical Placement: Quadratic Wirelength Model14m
Analytical Placement: Quadratic Placement26m
Analytical Placement: Recursive Partitioning18m
Analytical Placement: Recursive Partitioning Example16m
2개의 읽기 자료
Week 1 Overview10m
Week 1 Assignments10m
2
완료하는 데 6시간 필요

Technology Mapping

Technology Mapping! We omitted one critical step between logic and layout, the process of translating the output of synthesis -- which is NOT real gates in your technology library -- into real logic gates. The Tech Mapper performs this important step, and it is a surprisingly elegant algorithm involving recursive covering of a tree. Another place where knowing some practical computer science comes to the rescue in VLSI CAD.

...
6 videos (Total 102 min), 2 readings, 2 quizzes
6개의 동영상
Technology Mapping—Recursive Matching9m
Technology Mapping—Minimum Cost Covering16m
Technology Mapping—Detailed Covering Example14m
2개의 읽기 자료
Week 2 Overview10m
Week 2 Assignments10m
1개 연습문제
Problem Set #11h
3
완료하는 데 4시간 필요

ASIC Routing

Routing! You put a few million gates on the surface of the chip in some sensible way. What's next? Create the wires to connect them. We focus on Maze Routing, which is a classical and powerful technique with the virtue that one can "add" much sophisticated functionality on top of a rather simple core algorithm. This is also the topic for final (optional) programming assignment. Yes, if you choose, you get to route pieces of the industrial benchmarks we had you place in the placer software assignment.

...
9 videos (Total 145 min), 2 readings, 1 quiz
9개의 동영상
Maze Routing: Multi-Layer Routing12m
Maze Routing: Non-Uniform Grid Costs14m
Implementation Mechanics: How Expansion Works23m
Implementation Mechanics: Data Structures & Constraints18m
Implementation Mechanics: Depth First Search14m
From Detailed Routing to Global Routing15m
2개의 읽기 자료
Week 3 Overview10m
Week 3 Assignments10m
1개 연습문제
Problem Set #21h
4
완료하는 데 7시간 필요

Timing Analysis

You synthesized it. You mapped it. You placed it. You routed it. Now what? HOW FAST DOES IT GO? Oh, we need some new models, to talk about how TIMING works. Delay through logic gates and big networks of gates. New numbers to understand: ATs, RATs, SLACKS, etc. And some electrical details (minimal) to figure out how delays happen through the physical geometry of physical routed wires. All together this is the stuff of Static Timing Analysis (STA), which is a huge and important final "sign off" step in real ASIC design.

...
8 videos (Total 148 min), 2 readings, 2 quizzes
8개의 동영상
Logic-Level Timing: A Detailed Example and the Role of Slack10m
Logic-Level Timing: Computing ATs, RATs, Slacks, and Worst Paths26m
Interconnect Timing: Electrical Models of Wire Delay16m
Interconnect Timing: The Elmore Delay Model14m
Interconnect Timing: Elmore Delay Examples14m
2개의 읽기 자료
Week 4 Overview10m
Week 4 Assignments10m
1개 연습문제
Problem Set #31h
4.8
15개의 리뷰Chevron Right

VLSI CAD Part II: Layout의 최상위 리뷰

대학: ALOct 21st 2018

Great basic overview of the core design principles for EDA

강사

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Rob A. Rutenbar

Adjunct Professor
Department of Computer Science

일리노이대학교 어버너-섐페인캠퍼스 정보

The University of Illinois at Urbana-Champaign is a world leader in research, teaching and public engagement, distinguished by the breadth of its programs, broad academic excellence, and internationally renowned faculty and alumni. Illinois serves the world by creating knowledge, preparing students for lives of impact, and finding solutions to critical societal needs. ...

자주 묻는 질문

  • 강좌에 등록하면 바로 모든 비디오, 테스트 및 프로그래밍 과제(해당하는 경우)에 접근할 수 있습니다. 상호 첨삭 과제는 이 세션이 시작된 경우에만 제출하고 검토할 수 있습니다. 강좌를 구매하지 않고 살펴보기만 하면 특정 과제에 접근하지 못할 수 있습니다.

  • 수료증을 구매하면 성적 평가 과제를 포함한 모든 강좌 자료에 접근할 수 있습니다. 강좌를 완료하면 전자 수료증이 성취도 페이지에 추가되며, 해당 페이지에서 수료증을 인쇄하거나 LinkedIn 프로필에 수료증을 추가할 수 있습니다. 강좌 콘텐츠만 읽고 살펴보려면 해당 강좌를 무료로 청강할 수 있습니다.

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