학생용

Learning to speak VHDL (Intro)

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강의 계획서 보기

배우게 될 기술

Writing Code in Verilog, Simulating FPGA Designs, Designing FPGA Logic, Designing Test Benches, Writing code in VHDL

검토

4.3(344개의 평가)
  • 5 stars
    56.97%
  • 4 stars
    30.23%
  • 3 stars
    6.68%
  • 2 stars
    2.61%
  • 1 star
    3.48%
KP
2020년 10월 27일

I think this is a good start in learning how to write VHDL and Verilog.\n\nI would like to see a next level course or recommendations for further writing code.

R
2020년 7월 30일

The course helped in showing the different styles of the Verilog and VHDL coding.\n\nUnderstood the advantages of Verilog and VHDL in real life applications

수업에서
VHDL Logic Design Techniques

강사:

  • Placeholder

    Timothy Scherr

    Senior Instructor and Professor of Engineering Practice
  • Placeholder

    Benjamin Spriggs

    Lecturer and Scholar of Engineering Practice

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