Testbenches in Verilog

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강의 계획서 보기

배우게 될 기술

Writing Code in Verilog, Simulating FPGA Designs, Designing FPGA Logic, Designing Test Benches, Writing code in VHDL

검토

4(34개의 평가)
  • 5 stars
    50%
  • 4 stars
    26%
  • 3 stars
    6%
  • 2 stars
    6%
  • 1 star
    12%
WA

Mar 22, 2020

This course really great and have a lot of fun to learn FPGA Designs.

PD

Mar 18, 2020

Great course with in-depth explanations of HDL with Verilog and VHDL

수업에서
Verilog and System Verilog Design Techniques

강사:

  • Timothy Scherr

    Timothy Scherr

    Senior Instructor and Professor of Engineering Practice
  • Benjamin Spriggs

    Benjamin Spriggs

    Lecturer and Scholar of Engineering Practice

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