The Programming Assignments need to be more elaborate, things like reset is active low or active high and more details should be mentioned.

The course is good. It will enhance your vhdl and verilog skills but there are some places where i found insufficient details.

FIFO assignments in both Verilog and VHDL should define purpose of all the internal nets and registers listed in the problem.

Siento que faltan mas ejemplos y practicas, y en cuanto al apartado de lenguaje Verilog falta explicar aun mas sintaxis

Teaching methodology requires a lot more improvement. Assignments are challenging and its nice to try.

this course is given good idea of Hardware Description Language and i understood the concepts well.

Course content is moderate. But also have complexity level higher for a beginner.

its a very nice course. Its help me a lot to understand the basic of fpga.

A very engaging course to do for beginners having fundamentals strong.

Explanations are not that good for some circuits like memory

There should have been more examples of problems.

a big thank you to all the professiors

Concise, practical and useful

It should be more elaborative

BEST FOR THE BASIC

good

The course is OK, but the videos are terrible. The presenters do nothing more than just read the slides as they appear, which are sometimes just a page of code. In the VHDL section, I believe the presenter is seeing the material for the first time. I ended up just turning the audio off and treating the videos as a slide deck, which worked quite well. The assignments were fun.

I​nteresting course but exercises shall be reworked as sometimes it's not clear what is the expected output so we end up guessing via the testbench. Another issue is that some half backed quizzes prevent you from practicing the exercises until you pass even though practicing is key to understand the concepts...

this course need a person who knows before the basics of both VHDL/Verilog. because i know some basics of VHDL i understood its part but verilog was a little bit hard to me to understand it

Verilog part is explained very well but VHDL part completely unsatisfied.

Very introductory. Verilog and VHDL exercises are copied.

Innovative teaching, but very poor assignments

A decent introduction to HDL.

Teaching could be better.

good