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Hardware Description Languages for FPGA Design(으)로 돌아가기

콜로라도 대학교 볼더 캠퍼스의 Hardware Description Languages for FPGA Design 학습자 리뷰 및 피드백

469개의 평가
131개의 리뷰

강좌 소개

This course can also be taken for academic credit as ECEA 5361, part of CU Boulder’s Master of Science in Electrical Engineering degree. Hardware Description Languages for Logic Design enables students to design circuits using VHDL and Verilog, the most widespread design methods for FPGA Design. It uses natural learning processes to make learning the languages easy. Simple first examples are presented, then language rules and syntax, followed by more complex examples, and then finally use of test bench simulations to verify correctness of the designs. Lecture presentations are reinforced by many programming example problems so that skill in the languages is obtained. After completing this course, each student will have fundamental proficiency in both languages, and more importantly enough knowledge to continue learning and gaining expertise in Verilog and VHDL on their own....

최상위 리뷰


2021년 6월 6일

I really liked this course . if someone wants to know how digital circuits are made inside of computer then this course could be proven as turning point in his way of learning .


2022년 2월 20일

There are so much use cases that i can apply in my life. thanks so much for giving the psychology know how into the lecture to help us in understanding the root course

필터링 기준:

Hardware Description Languages for FPGA Design의 131개 리뷰 중 101~125

교육 기관: harsh

2020년 5월 15일

The Programming Assignments need to be more elaborate, things like reset is active low or active high and more details should be mentioned.

교육 기관: Rishi J

2020년 9월 4일

The course is good. It will enhance your vhdl and verilog skills but there are some places where i found insufficient details.

교육 기관: Aishwarya S

2020년 5월 7일

FIFO assignments in both Verilog and VHDL should define purpose of all the internal nets and registers listed in the problem.

교육 기관: Julio T A

2021년 4월 2일

Siento que faltan mas ejemplos y practicas, y en cuanto al apartado de lenguaje Verilog falta explicar aun mas sintaxis

교육 기관: Raghul R

2020년 6월 25일

Teaching methodology requires a lot more improvement. Assignments are challenging and its nice to try.


2020년 5월 14일

this course is given good idea of Hardware Description Language and i understood the concepts well.

교육 기관: Muhammad Z Y

2020년 4월 7일

Course content is moderate. But also have complexity level higher for a beginner.

교육 기관: Uzair A

2020년 10월 9일

its a very nice course. Its help me a lot to understand the basic of fpga.

교육 기관: Apoorva S

2020년 5월 25일

A very engaging course to do for beginners having fundamentals strong.

교육 기관: Yuvraj S R

2020년 5월 18일

Explanations are not that good for some circuits like memory

교육 기관: Sourav N

2020년 9월 18일

There should have been more examples of problems.

교육 기관: Mohamed C

2020년 4월 30일

a big thank you to all the professiors

교육 기관: Engels M

2021년 12월 3일

Concise, practical and useful

교육 기관: Prakash K R

2020년 6월 24일

It should be more elaborative


2020년 6월 7일


교육 기관: J S

2020년 8월 5일


교육 기관: Adriel K

2022년 3월 16일

The course is OK, but the videos are terrible. The presenters do nothing more than just read the slides as they appear, which are sometimes just a page of code. In the VHDL section, I believe the presenter is seeing the material for the first time. I ended up just turning the audio off and treating the videos as a slide deck, which worked quite well. The assignments were fun.

교육 기관: Julien T

2021년 12월 7일

I​nteresting course but exercises shall be reworked as sometimes it's not clear what is the expected output so we end up guessing via the testbench. Another issue is that some half backed quizzes prevent you from practicing the exercises until you pass even though practicing is key to understand the concepts...

교육 기관: Islam E

2020년 5월 31일

this course need a person who knows before the basics of both VHDL/Verilog. because i know some basics of VHDL i understood its part but verilog was a little bit hard to me to understand it

교육 기관: Harsh A

2020년 6월 15일

Verilog part is explained very well but VHDL part completely unsatisfied.

교육 기관: Sachin A

2020년 4월 21일

Very introductory. Verilog and VHDL exercises are copied.

교육 기관: Sakshat R

2020년 5월 28일

Innovative teaching, but very poor assignments

교육 기관: Samuel C

2020년 8월 14일

A decent introduction to HDL.

교육 기관: Pushkar A

2020년 9월 30일

Teaching could be better.

교육 기관: JYOTI S S

2021년 7월 11일