About this Course
2,147

100% 온라인

지금 바로 시작해 나만의 일정에 따라 학습을 진행하세요.

탄력적인 마감일

일정에 따라 마감일을 재설정합니다.

중급 단계

This course is aimed at students with prior programming experience and a desire to understand computation approaches to problem solving.

완료하는 데 약 12시간 필요

권장: 4-10 hours/week...

영어

자막: 영어

귀하가 습득할 기술

Programming PrinciplesComputer ArchitectureProgramming Language Concepts

100% 온라인

지금 바로 시작해 나만의 일정에 따라 학습을 진행하세요.

탄력적인 마감일

일정에 따라 마감일을 재설정합니다.

중급 단계

This course is aimed at students with prior programming experience and a desire to understand computation approaches to problem solving.

완료하는 데 약 12시간 필요

권장: 4-10 hours/week...

영어

자막: 영어

강의 계획 - 이 강좌에서 배울 내용

1
완료하는 데 2시간 필요

Familizarize youself with FPGA technologies

From the mid-1980s, reconfigurable computing has become a popular field due to the FPGA technology progress. An FPGA is a semiconductor device containing programmable logic components and programmable interconnects but no instruction fetch at run time, that is, FPGAs do not have a program counter. In most FPGAs, the logic components can be programmed to duplicate the functionality of basic logic gates or functional Intellectual Properties (IPs). FPGAs also include memory elements composed of simple flip-flops or more complex blocks of memories. Hence, FPGA has made possible the dynamic execution and configuration of both hardware and software on a single chip. This module provides a detailed description of FPGA technologies starting from a general description down to the discussion on the low-level configuration details of these devices, to the bitstream composition and the description of the configuration registers....
9 videos (Total 57 min), 2 quizzes
9개의 동영상
FPGA-based systems and reconfiguration4m
Programmable System-on-Multiple Chips7m
Programmable System-on-Chips4m
FPGAs main building blocks7m
How to program an FPGA: bitstream and configuration5m
How to program an FPGA: system description and physical design7m
CAD Tools for FPGA-based systems design6m
An introuction to the SDx development environment9m
2개 연습문제
QUIZ 140m
QUIZ 230m
2
완료하는 데 3시간 필요

A bird's eye view on SDAccel

The Xilinx SDAccel Development Environment let the user express kernels in OpenCL C, C++ and RTL (as an example we can think of, SystemVerilog, Verilog or VHDL) to run on Xilinx programmable platforms. The programmable platform is composed of (1) the SDAccel Xilinx Open Code Compiler (XOCC), (2) a Device Support Archive (DSA) which describes the hardware platform, (3) a software platform, (4) an accelerator board, and5. last but not least, the SDAccel OpenCL runtime. Within this module, after an introduction to OpenCL, we are going to see how this language has been sued in SDAccel and the main "components" of this toolchain....
7 videos (Total 37 min), 1 reading, 1 quiz
7개의 동영상
An introduction to SDAccel and the OpenCL-based flow5m
OpenCL computational model: global and local sizes4m
Not only OpenCL! The Rationale behind the RTL and C flows5m
SDAccel memory model5m
SDAccel "emulations"5m
SDAccel runtime4m
1개의 읽기 자료
SDAccel Environment Programmers Guide
1개 연습문제
QUIZ 330m
3
완료하는 데 3시간 필요

On how to optmize your system

Within this module, Before getting into the optimisation, we will first understand how an FPGA is working, also from a computational point of view. Although the traditional FPGA design flow is more similar to a regular IC than a processor, an FPGA provides significant cost advantages in comparison to an IC development effort and offers the same level of performance in most cases. Another advantage of the FPGA when compared to the IC is its ability to be dynamically reconfigured. This process, which is the same as loading a program in a processor, can affect part or all of the resources available in the FPGA fabric. When compared with processor architectures, the structures that comprise the FPGA fabric enable a high degree of parallelism in application execution. The custom processing architecture generated by SDAccel for an OpenCL kernel presents a different execution paradigm. This must be taken into account when deciding to port an application from a processor to an FPGA. To better understand such a scenario we will briefly compare a processor sequential execution with the intrinsic parallel nature of an FPGA implementation. Furthermore, within this module we are going to familiarise ourselves with the application optimisation flow.The Xilinx SDAccel Environment is a complete Software Development Environment, for creating, compiling, and optimising OpenCL applications with the objective of being accelerated on Xilinx FPGAs. From a designer perspective we can organise the flow for optimising an application in the SDAccel Environment as a three phases flow. Those three phases are: (1) baselining functionalities and performance, (2) optimising data movement and (3) optimising kernel computation...
5 videos (Total 37 min), 1 reading, 1 quiz
5개의 동영상
FPGA Parallelism vs Processor Architecture 1/27m
FPGA Parallelism vs Processor Architecture 2/28m
Scheduling, Pipelining, and Dataflow8m
Application Optimization Flow6m
1개의 읽기 자료
SDAccel Environment Profiling and Optimisation Guide30m
1개 연습문제
QUIZ 430m
완료하는 데 5시간 필요

Optimize your system via SDAccel

In this module we will provide a bird's eye view on the available SDAccel optimisations. The presented optimisations are not the only available ones, but they are more a list of recommendations to optimise the performance of an OpenCL application that have to be used as a starting point for ideas to consider or investigate further. Within this context we will organise these “recommendations” in three sets of optimisations: (1) arithmetic optimisations, (2) data-related optimisations, and finally (3) memory-related optimisations....
6 videos (Total 34 min), 2 readings, 1 quiz
6개의 동영상
Interface optimizations: Overall context and an overview of a typical target architecture6m
Interface optimizations: a first example5m
Burst data transfer3m
Using full AXI data width4m
Using multiple memory banks3m
2개의 읽기 자료
SDAccel Environment Profiling and Optimisation Guide
Sources Codes30m
1개 연습문제
QUIZ 530m
4
완료하는 데 4시간 필요

Other optimizations

After an overall description of possibile optimisations, within this module we will focus on four specific optimisations (1) loop unrolling, (2) loop pipelining, (3) array partitioning and (4) the host optimisations. First, we will describe loop unrolling which means to unroll the loop iterations so that, the number of iterations of the loop reduces, and the loop body performs extra computation. This technique allows to expose additional instruction level parallelism that Vivado HLS can exploit to implement the final hardware design. After that we will present the loop pipelining optimisation, where we will move from a sequential execution of the loop iterations to a pipelined execution in which the loop iterations are overlapped in time. After that we will present the array partitioning optimisation which allows to optimise the usage of BRAM resources in order to improve the performance of the kernel. Finally, at the end of this module we are going to discuss optimisations related to the host system that is responsible for transferring the data to and from the FPGA board, as well as to send the command to start the execution of a kernel....
6 videos (Total 43 min), 2 readings, 1 quiz
6개의 동영상
Kernel optimization: loop unrolling 2/26m
Kernel optimization: loop pipelining9m
Kernel optimization: array partitioning 1/28m
Kernel optimization: array partitioning 2/27m
Host optimizations5m
2개의 읽기 자료
SDAccel Environment Profiling and Optimisation Guide30m
Source Codes30m
1개 연습문제
QUIZ 630m
완료하는 데 3시간 필요

An introduction to FPGA-augmented cloud infrastructures

...
3 videos (Total 14 min), 1 reading, 1 quiz
3개의 동영상
An introduction to SDAccel and the AWS EC2 F1 instances8m
Closing remarks and future directions1m
1개의 읽기 자료
A Scalable FPGA Design for Cloud N-Body Simulation
1개 연습문제
QUIZ 720m

강사

Avatar

Marco Domenico Santambrogio

Associate Professor
DEIB - Dept. of Electronics, Information and Bioengineering

밀라노 국립건축대학 정보

Politecnico di Milano is a scientific-technological University, which trains engineers, architects and industrial designers. From 2014 Politecnico di Milano started the release of several MOOCs, developed by the service for digital learning METID (Methods and Innovative Technologies for Learning), giving everybody the chance to enhance personal skills....

자주 묻는 질문

  • 강좌에 등록하면 바로 모든 비디오, 테스트 및 프로그래밍 과제(해당하는 경우)에 접근할 수 있습니다. 상호 첨삭 과제는 이 세션이 시작된 경우에만 제출하고 검토할 수 있습니다. 강좌를 구매하지 않고 살펴보기만 하면 특정 과제에 접근하지 못할 수 있습니다.

  • 수료증을 구매하면 성적 평가 과제를 포함한 모든 강좌 자료에 접근할 수 있습니다. 강좌를 완료하면 전자 수료증이 성취도 페이지에 추가되며, 해당 페이지에서 수료증을 인쇄하거나 LinkedIn 프로필에 수료증을 추가할 수 있습니다. 강좌 콘텐츠만 읽고 살펴보려면 해당 강좌를 무료로 청강할 수 있습니다.

궁금한 점이 더 있으신가요? 학습자 도움말 센터를 방문해 보세요.